library ieee;
use ieee.std_logic_1164.all;

--Counter Module will clear when clr is 1
entity counterModule is
	port (
		input, en, clr, clk: in bit;
		output : out bit
	);
end entity counterModule;

architecture STRUCTURAL of counterModule is
	
	component mux2to1
	
	port(I0,I1,S : in bit;
		F : out bit
	);
	
	end component; 
	
	component jkFlipFlop
	
	port(j,k,clk : in bit;
		q,qnot : out bit
	);
	
	end component; 
	
	component and2
	
	port(a,b : in bit;
		z : out bit
	);
	
	end component;
	
		
	for all : mux2to1 use entity work.mux2to1;
	for all : jkFlipFlop use entity work.jkFlipFlop;
	for all : and2 use entity work.and2;
	
	signal sigVec : bit_vector(2 downTo 0);	
	signal gnd : bit := '0';
	
begin

	AND0 : and2  port map(en, input, sigVec(0));
	
	--The Mux will produce gnd if clr is high
	MUX : mux2to1 port map(sigVec(0), gnd, clr, sigVec(1)); 
	
	JK : jkFlipFlop  port map(sigVec(1), en, clk, sigVec(2));	
	
	output <= sigVec(2);

end STRUCTURAL;